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a25lq080 series 8mbit, 3v suspend/resume, dual/q uad-i/o serial flash memory with 100mhz uniform 4kb sectors (april, 2016, version 1.0) amic technology corp. amic reserves the right to change products and specifications discussed herein without notice. document title 8mbit, 3v suspend/resume, dual/quad-i/o serial flash memo ry with 100mhz uniform 4kb sectors revision history rev. no. history issue date remark 1.0 final version issue april 1, 2016 final
a25lq080 series 8mbit, 3v suspend/resume, dual/q uad-i/o serial flash memory with 100mhz uniform 4kb sectors (april, 2016, version 1.0) 1 amic technology corp. features ? family of serial flash memories - a25lq080: 8m-bit /2m-byte ? flexible sector architecture with 4kb sectors - sector erase (4k-bytes) in 70ms (typical) - block erase (64k-bytes) in 0.5s (typical) - program/erase suspend & resume ? page program (up to 256 bytes) in 1.5ms (typical) ? 2.7 to 3.6v single supply voltage ? dual input / output instructio ns resulting in an equivalent clock frequency of 200mhz: - fast_read_dual_output instruction - fast_read_dual_input_output instruction - dual input fast program (difp) instruction ? quad input / output instructions resulting in an equivalent clock frequency of 400mhz: - fast_read_quad_ output instruction - fast_read_quad_input_output instruction - quad input fast program (qifp) instruction ? spi bus compatible serial interface ? 100mhz clock rate (maximum) ? deep power-down mode 15a (max.) ? advanced protection features - software and hardware write-protect - top/bottom, 4kb complement array protection ? additional 64-byte user-lockable, one-time programmable (otp) area ? 8mbit flash memory - uniform 4-kbyte sectors - uniform 64-kbyte blocks ? electronic signatures - jedec standard two-byte signature a25lq080: (4014h) - res instruction, one-byte, signature, for backward compatibility a25lq080: (13h) ? package options - 8-pin sop (150/209mil), 8-pin dip (300mil) or 8-pin wson (6*5mm) - all pb-free (lead-free) products are rohs compliant general description the a25lq080 is 8m bit serial flash memory, with advanced write protection mechanisms, accessed by a high speed spi-compatible bus. the memory can be programmed 1 to 256 bytes at a time, using the page program instruction. the memory is organized as 16 blocks, each containing 16 sectors. each sector is comp osed of 16 pages. each page is 256 bytes wide. thus, the whole memory can be viewed as consisting of 4,096 pages, or 1,048,576 bytes. the whole memory can be erased using the chip erase instruction, a block at a time, us ing block erase instruction, or a sector at a time, using the sector erase instruction. pin configurations ? sop8 connections ? dip8 connections ? wson8 connections a25lq080 v cc c do (io 1 ) di (io 0 ) s w (io 2 ) hold (io 3 ) v ss 1 8 2 7 3 6 4 5 a25lq080 1 2 3 4 8 7 6 5 do (io 1 ) s w (io 2 ) v ss v cc c di (io 0 ) hold (io 3 ) a25lq080 v cc c do (io 1 ) di (io 0 ) s w (io 2 ) hold (io 3 ) v ss 1 8 2 7 3 6 4 5
a25lq080 series (april, 2016, version 1.0) 2 amic technology corp. pin descriptions notes: (1) io 0 and io 1 are used for dual and quad instructions (2) io 0 ~ io 3 are used for quad instructions block diagram i/o shift register control logic high voltage generator address register and counter 256 byte data buffer status register x decoder 256 byte (page size) y decoder size of the memory area di (io 0 ) do (io 1 ) c 0000ffh 000000h hold (io 3 ) w (io 2 ) s fffffh (8m) 64 otp bytes pin no. pin name i/o description 1 s i chip select input 2 do (io 1 ) i/o data output (d ata input output 1) (1) 3 w (io 2 ) i/o write protect input (data input output 2) (2) 4 v ss ground 5 di (io 0 ) i/o data input (data input output 0) (1) 6 c i serial clock input 7 hold (io 3 ) i/o hold input (data input output 3) (2) 8 v cc power supply
a25lq080 series (april, 2016, version 1.0) 3 amic technology corp. pin description chip select ( s ) the spi chip select ( s ) pin enables and disables device operation. when chip select ( s ) is high the device is deselected and the serial data output (do, or io 0 , io 1 , io 2 , io 3 ) pins are at high impedanc e. when deselected, the devices power consumption wi ll be at standby levels unless an internal erase, program or writ e status register cycle is in progress. when chip select ( s ) is brought low the device will be selected, power consumption will increase to active levels and instructions can be writt en to and data read from the device. after power-up, chip select ( s ) must transition from high to low before a new instruction will be accepted. serial data input, output and ios (di, do and io 0 , io 1 , io 2 , io 3 ) the a25lq080 support standard spi, dual spi and quad spi operation. standard spi instructions use the unidirectional di (input) pin to serially write instructions, addresses or data to the device on the rising edge of the serial clock (c) input pin. standard spi also uses the unidirectional do (output) to r ead data or status from the device on the falling edge of serial clock (c). dual and quad spi instruction use the bidirectional io pins to serially write instructions, addresses or data to the device on the rising edge of serial cl ock (c) and read data or status from the device on the falling edge of serial clock (c). quad spi instructions require the non-volatile quad enable bit (qe) in status register-2 to be set. when qe=1 the write protect ( w ) pin becomes io 2 and hold ( hold ) pin becomes io 3 . write protect ( w ) the write protect ( w ) pin can be used to prevent the status register from being written. used in conjunction with the status register?s block protect (cmp, sec, tb, bp2, bp1 and bp0) bits and status regist er protect (srp0) bit, a portion or the entire memory array can be hardware protected. the write protect ( w ) pin is active low. when the qe bit of st atus register-2 is set for quad i/o, the write protect ( w ) pin (hardware write protect) function is not available since this pin is used for io 2 . see the pin configuration for quad i/o operation. hold ( hold ) the hold ( hold ) pin allows the device to be paused while it is actively selected. when hold ( hold ) pin is brought low, while chip select ( s ) pin is low, the do pin will be at high impedance and signals on the di and serial clock (c) pins will be ignored (don?t care). when hold ( hold ) pin is brought high, device operation can resume. the hold function can be useful when multiple devices are sharing the same spi signals. the hold ( hold ) pin is active low. when the qe bit of status regi ster-2 is set for quad i/o. the hold ( hold ) pin function is not available since this pin is used for io 3 . see the pin confi guration for quad i/o operation. serial clock (c) the spi serial clock input (c) pin provides the timing for serial input and output operations.
a25lq080 series (april, 2016, version 1.0) 4 amic technology corp. spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: ? cpol=0, cpha=0 ? cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from the falling edge of serial clock (c). the difference between the two modes, as shown in figure 1, is the clock polarity when the bus master is in stand-by mode and not transferring data: ? c remains at 0 for (cpol=0, cpha=0) ? mode 0 ? c remains at 1 for (cpol=1, cpha=1) ? mode 3 figure 1. spi modes supported msb msb c c dio do 00 1 1 cpol cpha mode 0 mode 3
a25lq080 series (april, 2016, version 1.0) 5 amic technology corp. spi operations standard spi instructions the a25lq080 is accessed through an spi compatible bus consisting of four signals: serial clock (c), chip select ( s ), serial data input (di), and serial data output (do). standard spi instructions use the di input pin to serially write instructions, addresses or data to the device on the rising edge of serial clock (c). the do output pin is used to read data or status from the device on the falling edge of serial clock (c). dual spi instructions the a25lq080 supports dual spi operation when using the ?fast_read_dual_output and fast_read_dual_ input_output? (3b and bb hex) instructions. these instructions allow data to be transferred to or from the device at two to three times the rate of ordinary serial flash devices. the dual read instructions are ideal for quickly downloading code to ram upon power-up (code-shadowing) or for executing non-speed-critical code directly from the spi bus (xip). when using dual spi instructions the di and do pins become bidirectional i/o pins; io 0 and io 1 . quad spi instructions the a25lq080 supports quad spi operation when using the ?fast_read_quad_output? (6b hex) and ?fast_read_quad_input_output? (eb hex) instructions. this instruction allows data to be transferred to or from the device four to six times the rate of ordinary serial flash. these 2 instructions offer a significant improvement in continuous and random access transfer rates allowing fast code-shadowing to ram or execution directly from the spi bus (xip). when using quad spi instructions the di and do pins become bi-directional io 0 and io 1 , and the w and hold pins become io 2 and io 3 respectively. quad spi instructions require the non-volatile quad enable bit (qe) in status register-2 to be set. hold condition the hold ( hold ) signal is used to pause any serial communications with the device without resetting the clocking sequence. however, taking this signal low does not terminate any write status register, program or erase cycle that is currently in progress. the hold function is only available for standard spi and dual spi operation, not during quad spi. to enter the hold condition, the device must be selected, with chip select ( s ) low. the hold condition starts on the falling edge of the hold ( hold ) signal, provided that this coincides with serial clock (c) being low (as shown in figure 2.). the hold condition ends on the rising edge of the hold ( hold ) signal, provided that this coincides with serial clock (c) being low. if the falling edge does not coincide with serial clock (c) being low, the hold condition starts after serial clock (c) next goes low. similarly, if the rising edge does not coincide with serial clock (c) being low, the hold condition ends after serial clock (c) next goes low. this is shown in figure 2. during the hold condition, the serial data output (do) is high impedance, and serial data input (di) and serial clock (c) are don?t care. normally, the device is kept selected, with chip select ( s ) driven low, for the whole duration of the hold condition. this is to ensure that the state of the internal logic remains unchanged from the moment of entering the hold condition. if chip select ( s ) goes high while the device is in the hold condition, this has the effect of resetting the internal logic of the device. to restart communication with the device, it is necessary to drive hold ( hold ) high, and then to drive chip select ( s ) low. this prevents the device from going back to the hold condition. figure 2. hold condition activation hold condition (standard use) hold c hold condition (non-standard use)
a25lq080 series (april, 2016, version 1.0) 6 amic technology corp. operating features page programming to program one data byte, two instructions are required: write enable (wren), which is one byte, and a page program (pp) sequence, which consists of four bytes plus data. this is followed by the internal program cycle (of duration t pp ). to spread this overhead, the page program (pp) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. dual input fast program the dual input fast program (difp) instruction makes it possible to program up to 256 bytes using two input pins at the same time (by changing bits from 1 to 0). for optimized timings, it is recommended to use the dual input fast program (difp) instruction to program all consecutive targeted bytes in a single sequence rather to using several dual input fast program (difp) sequences each containing only a few bytes. quad input fast program the quad input fast program (qifp) instruction makes it possible to program up to 256 bytes using four input pins (io 3 , io 2 , io 1 , and io 0 ) at the same time (by changing bits from 1 to 0). for optimized timings, it is recommended to use the quad input fast program (qifp) instruction to program all consecutive targeted bytes in a single sequence rather to using several quad input fast program (qifp) sequences each containing only a few bytes. sector erase, block erase, and chip erase the page program (pp) instruction, dual input fast program (difp) instruction, and quad input fast program (qifp) instruction allow bits to be reset from 1 to 0. before this can be applied, the bytes of memory need to have been erased to all 1s (ffh). this can be achieved, a sector at a time, using the sector erase (se) instruction, a block at a time, using the block erase (be) instruction, or throughout the entire memory, using the chip erase (ce) instruction. this starts an internal erase cycle (of duration t se, t be, or t ce ). the erase instruction must be preceded by a write enable (wren) instruction. polling during a write, program or erase cycle a further improvement in the time to write status register (wrsr), program otp (potp), program (pp, difp, qifp), or erase (se, be, or ce) can be achieved by not waiting for the worst case delay (t w , t pp , t se , t be , t ce ). the write in progress (wip) bit is provided in the status register so that the application program can monitor its value, polling it to establish when the previous write cycle, program cycle or erase cycle is complete. active power, stand-by power and deep power-down modes when chip select ( s ) is low, the device is enabled, and in the active power mode. when chip select ( s ) is high, the device is disabled, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). the device then goes in to the stand-by power mode. the device consumption drops to i cc1 . the deep power-down mode is entered when the specific instruction (the deep power-down mode (dp) instruction) is executed. the device consumption drops further to i cc2 . the device remains in this mode until another specific instruction (the release from deep power-down mode and read electronic signature (res) instruction) is executed. all other instructions are ignored while the device is in the deep power-down mode. this can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent write, program or erase instructions. status register the status register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. see read status register (rdsr) for a detailed description of the status register bits. protection modes the environments where non-volatile memory devices are used can be very noisy. no spi device can operate correctly in the presence of excessive noise. to help combat this, the a25lq080 boasts the following data protection mechanisms: ? power-on reset and an internal timer (t puw ) can provide protection against inadvertent changes while the power supply is outside the operating specification. ? program, erase and write status register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. ? all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit. this bit is returned to its reset state by the following events: - power-up - write disable (wrdi) instruction completion - write status register (wrsr) instruction completion - program otp (potp) instruction completion - page program (pp) instruction completion - dual input fast program (difp) instruction completion - quad input fast program (qifp) instruction completion - sector erase (se) instruction completion - block erase (be) instruction completion - chip erase (ce) instruction completion ? the block protect (bp2, bp1, bp0) bits conjunction with sector protect (sec) bit , top/bottom (tb) bit and complement protect (cmp) bit allow part of the memory to be configured as read-only. this is the software protected mode (spm). ? the write protect ( w ) signal allows the block protect (bp2, bp1, bp0) bits, sector protect (sec) bit, top/bottom (tb) bit, all protect (apt), complement protect (cmp) bit and status register protect (srp0) bit to be protected. this is the hardware protected mode (hpm). ? in addition to the low power consumption feature, the deep power-down mode offers extra software protection from inadvertent write, program and erase instructions, as all instructions are ignored except one particular instruction (the release from deep power-down instruction).
a25lq080 series (april, 2016, version 1.0) 7 amic technology corp. table 1-1. protected area sizes (cmp=0) a25lq080 status register content (8m-bit) memory protection sec tb bp2 bp1 bp0 block(s) addresses density(byte) portion x x 0 0 0 none none none none 0 0 0 0 1 15 f0000h ? fffffh 64kb upper 1/16 0 0 0 1 0 14 ? 15 e0000h ? fffffh 128kb upper 1/8 0 0 0 1 1 12 ? 15 c0000h ? fffffh 256kb upper 1/4 0 0 1 0 0 8 ? 15 80000h ? fffffh 512kb upper 1/2 0 0 1 0 1 0 ? 15 000 00h ? fffffh 1mb all 0 1 0 0 1 0 000000h ? 0ffffh 64kb lower 1/16 0 1 0 1 0 0 ? 1 000000h ? 1ffffh 128kb lower 1/8 0 1 0 1 1 0 ? 3 000000h ? 3ffffh 256kb lower 1/4 0 1 1 0 0 0 ? 7 000000h ? 7ffffh 512kb lower 1/2 0 1 1 0 1 0 ? 15 000000h ? fffffh 1mb all x x 1 1 x 0 ? 15 000000h ? fffffh 1mb all 1 0 0 0 1 15 ff000h ? fffffh 4kb top block 1 0 0 1 0 15 fe000h ? fffffh 8kb top block 1 0 0 1 1 15 fc000h ? fffffh 16kb top block 1 0 1 0 x 15 f8000h ? fffffh 32kb top block 1 1 0 0 1 0 000000h ? 00fffh 4kb bottom block 1 1 0 1 0 0 000000h ? 01fffh 8kb bottom block 1 1 0 1 1 0 000000h ? 03fffh 16kb bottom block 1 1 1 0 x 0 000000h ? 07fffh 32kb bottom block note: 1. x = don?t care 2. if any erase or program command specifies a memory region that contains protected data portion, this command will be ignored.
a25lq080 series (april, 2016, version 1.0) 8 amic technology corp. table 1-2. protected area sizes (cmp=1) a25lq080 status register content (8m-bit) memory protection sec tb bp2 bp1 bp0 block(s) addresses density(byte) portion x x 0 0 0 0 ? 15 000000h ? fffffh 1mb all 0 0 0 0 1 0 ? 14 000000h ? effffh 960kb lower 15/16 0 0 0 1 0 0 ? 13 000000h ? dffffh 896kb lower 7/8 0 0 0 1 1 0 ? 11 000000h ? bffffh 768kb lower 3/4 0 0 1 0 0 0 ? 7 000000h ? 7ffffh 512kb lower 1/2 0 0 1 0 1 0 ? 7 000000h ? 7ffffh 512kb lower 1/2 0 0 1 1 0 0 ? 7 000000h ? 7ffffh 512kb lower 1/2 0 0 1 1 1 none none none none 0 1 0 0 1 1 ? 15 010000h ? fffffh 960kb upper 15/16 0 1 0 1 0 2 ? 15 020000h ? fffffh 896kb upper 7/8 0 1 0 1 1 4 ? 15 040000h ? fffffh 768kb upper 3/4 0 1 1 0 0 8 ? 15 080000h ? fffffh 512kb lower 1/2 0 1 1 0 1 8 ? 15 080000h ? fffffh 512kb lower 1/2 0 1 1 1 0 8 ? 15 080000h ? fffffh 512kb lower 1/2 0 1 1 1 1 none none none none 1 0 0 0 1 0 ? 15 000000h ? fefffh 1020kb lower 255/256 1 0 0 1 0 0 ? 15 000000h ? fdfffh 1016kb lower 127/128 1 0 0 1 1 0 ? 15 000000h ? fbfffh 1008kb lower 63/64 1 0 1 1 0 0 ? 15 000000h ? f7fffh 992kb lower 31/32 1 0 1 1 1 none none none none 1 1 0 0 1 0 ? 15 001000h ? fffffh 1020kb upper 255/256 1 1 0 1 0 0 ? 15 002000h ? fffffh 1016kb upper 127/128 1 1 0 1 1 0 ? 15 004000h ? fffffh 1008kb upper 63/64 1 1 1 1 0 0 ? 15 008000h ? fffffh 992kb upper 31/32 1 1 1 1 1 none none none none note: 1. x = don?t care 2. if any erase or program command specifies a memory region that contains protected data portion, this command will be ignored.
a25lq080 series (april, 2016, version 1.0) 9 amic technology corp. memory organization the memory is organized as: ? 1,048,576 bytes (8 bits each) ? 16 blocks (64 kbytes each) ? 256 sectors (4 kbytes each) ? 4096 pages (256 bytes each) ? 64 bytes otp located outside the main memory array each page can be individually programmed (bits are programmed from 1 to 0). the device is sector, block, or chip erasable (bits are erased from 0 to 1) but not page erasable. table 2. memory organization a25lq080 address table block sector address range 255 ff000h fffffh ... ... ... 15 240 f0000h f0fffh 239 ef000h effffh ... ... ... 14 224 e0000h e0fffh 223 df000h dffffh ... ... ... 13 208 d0000h d0fffh 207 cf000h cffffh ... ... ... 12 192 c0000h c0fffh 191 bf000h bffffh ... ... ... 11 176 b0000h b0fffh 175 af000h affffh ... ... ... 10 160 a0000h a0fffh 159 9f000h 9ffffh ... ... ... 9 144 90000h 90fffh 143 8f000h 8ffffh ... ... ... 8 128 80000h 80fffh 127 7f000h 7ffffh ... ... ... 7 112 70000h 70fffh block sector address range 111 6f000h 6ffffh ... ... ... 6 96 60000h 60fffh 95 5f000h 5ffffh ... ... ... 5 80 50000h 50fffh 79 4f000h 4ffffh ... ... ... 4 64 40000h 40fffh 63 3f000h 3ffffh ... ... ... 3 48 30000h 30fffh 47 2f000h 2ffffh ... ... ... 2 32 20000h 20fffh 31 1f000h 1ffffh ... ... ... 1 16 10000h 10fffh 15 0f000h 0ffffh ... ... ... 4 04000h 04fffh 3 03000h 03fffh 2 02000h 02fffh 1 01000h 01fffh 0 0 00000h 00fffh
a25lq080 series (april, 2016, version 1.0) 10 amic technology corp. instructions all instructions, addresses and data are shifted in and out of the device, most significant bit first. serial data input(s) io 0 (io 1 , io 2 , io 3 ) is (are) sampled on the first rising edge of serial clock (c) after chip select ( s ) is driven low. then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input(s) io 0 (io 1 , io 2 , io 3 ), each bit being latched on the rising edges of serial clock (c). the instruction set is listed in table 3. every instruction sequence starts with a one-byte instruction code. depending on the instruction, this might be followed by address bytes, or by data bytes, or by dummy bytes (don?t care), or by a combination or none. in the case of a read data bytes (read), read data bytes at higher speed (fast_read), read data bytes at higher speed by dual output (fast_read_dual_output), read data bytes at higher speed by dual input and dual output (fast_read_dual_input_output) , read data bytes at higher speed by quad output (fast_read_quad _output), read data bytes at higher speed by quad input and quad output (fast_read_quad_input_output), read otp (rotp), read identification (rdid), read electronic manufacturer and device identification (rems), read status register (rdsr) or release from deep power-down, read device identification and read electronic signature (res) instruction, the shifted-in instruction se- quence is followed by a data-out sequence. chip select ( s ) can be driven high after any bit of the data-out sequence is being shifted out. in the case of a page program (pp), program otp (potp), dual input fast program (difp), quad input fast program (qifp), sector erase (se), blo ck erase (be), chip erase (ce), write status register (wrsr), write enable (wren), write disable (wrdi) or deep power-down (dp) instruction, chip select ( s ) must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. that is, chip select ( s ) must driven high when the number of clock pulses after chip select ( s ) being driven low is an exact multiple of eight. all attempts to access the memory array during a write status register cycle, program cycle or erase cycle are ignored, and the internal write status register cycle, program cycle or erase cycle continues unaffected.
a25lq080 series (april, 2016, version 1.0) 11 amic technology corp. table 3. instruction set instruction description one-byte instruction code address bytes dummy bytes data bytes wren write enable 0000 0110 06h 0 0 0 wrdi write disable 0000 0100 04h 0 0 0 rdsr-1 read status register-1 0000 0101 05h 0 0 1 to rdsr-2 read status register-2 0011 0101 35h 0 0 1 to wrsr write status register 0000 0001 01h 0 0 2 read read data bytes 0000 0011 03h 3 0 1 to fast_read read data bytes at higher speed 0000 1011 0bh 3 1 1 to fast_read_dual _output read data bytes at higher speed by dual output (1) 0011 1011 3bh 3 1 1 to (1) fast_read_dual _input_output read data bytes at higher speed by dual input and dual output (1)(2) 1011 1011 bbh 3 (2) 1 (2) 1 to (1) fast_read_quad _output read data bytes at higher speed by quad output (4) 0110 1011 6bh 3 1 1 to (4) fast_read_quad _input_output read data bytes at higher speed by quad input and quad output (3)(4) 1110 1011 ebh 3 (3) 1 (3) 1 to (4) rotp read otp (read 64 bytes of otp area) 0100 1011 4bh or 48h 3 1 1 to potp program otp (program 64 bytes of otp area) 0100 0010 42h 3 0 1 to 64 pp page program 0000 0010 02h 3 0 1 to 256 difp dual input fast program 1010 0010 a2h 3 0 1 to 256 (5) qifp quad input fast program 0011 0010 32h 3 0 1 to 256 (6) se sector erase 0010 0000 20h 3 0 0 be block erase 1101 1000 d8h or 52h 3 0 0 ce chip erase 1100 0111 c7h or 60h 0 0 0 dp deep power-down 1011 1001 b9h 0 0 0 rdid read device identification 1001 1111 9fh 0 0 1 to rems read electronic manufacturer & device identification 1001 0000 90h 1 (7) 2 1 to release from deep power-down, and read electronic signature 0 3 1 to res release from deep power-down 1010 1011 abh 0 0 0 hpm high performance mode 1010 0011 a3h 0 3 0 0111 0101 75h suspend program / erase suspend 1011 0000 b0h 0 0 0 0111 1010 7ah resume program / erase resume 0011 0000 30h 0 0 0 sfdp read sfdp 0101 1010 5ah 3 1 1 to 64
a25lq080 series (april, 2016, version 1.0) 12 amic technology corp. note: (1) dual output data io 0 = (d 6 , d 4 , d 2 , d 0 ) io 1 = (d 7 , d 5 , d 3 , d 1 ) (2) dual input address io 0 = (a22, a20, a18, a16, a14, a12, a10, a8, a6, a4, a2, a0, m6, m4, m2, m0) io 1 = (a23, a21, a19, a17, a15, a13, a11, a9, a7, a5, a3, a1, m7, m5, m3, m1) (3) quad input address io 0 = (a20, a16, a12, a8, a4, a0, m4, m0) io 1 = (a21, a17, a13, a9, a5, a1, m5, m1) io 2 = (a22, a18, a14, a10, a6, a2, m6, m2) io 3 = (a23, a19, a15, a11, a7, a3, m7, m3) (4) quad output data io 0 = (d 4 , d 0 , ?..) io 1 = (d 5 , d 1 , ?..) io 2 = (d 6 , d 2 , ?..) io 3 = (d 7 , d 3 , ?..) (5) dual input fast program input data io 0 = (d 6 , d 4 , d 2 , d 0 ) io 1 = (d 7 , d 5 , d 3 , d 1 ) (6) quad input fast program input data io 0 = (d 4 , d 0 , ?..) io 1 = (d 5 , d 1 , ?..) io 2 = (d 6 , d 2 , ?..) io 3 = (d 7 , d 3 , ?..) (7) add= (00h) will output manufacturer?s id first and add=(01h) will output device id first
a25lq080 series (april, 2016, version 1.0) 13 amic technology corp. write enable (wren) the write enable (wren) instruction (figure 3.) sets the write enable latch (wel) bit. the write enable latch (wel) bit must be set prior to every page program (pp), dual input fast program (difp), quad input fast program (qifp), program otp (potp), sector erase (se), block erase (be), and chip erase (ce) and write status register (wrsr) instruction. the write enable (wren) instruction is entered by driving chip select ( s ) low, sending the instruction code, and then driving chip select ( s ) high. figure 3. write enable (wren) instruction sequence s c di do high impedance instruction (06h) 01 23 45 67 write disable (wrdi) the write disable (wrdi) instruction (figure 4.) resets the write enable latch (wel) bit. the write disable (wrdi) instruction is entered by driving chip select ( s ) low, sending the instruction code, and then driving chip the write enable latch (wel) bit is reset under the following conditions: power-up write disable (wrdi) instruction completion write status register (wrsr) instruction completion page program (pp) instruction completion dual input fast program (difp) instruction completion quad input fast program (qifp) instruction completion program otp (potp) in struction completion sector erase (se) instruction completion block erase (be) instruction completion chip erase (ce) instruction completion figure 4. write disable (wrdi) instruction sequence s c di do high impedance instruction (04h) 01 23 45 67
a25lq080 series (april, 2016, version 1.0) 14 amic technology corp. read status register (rdsr) the read status register (rdsr) instruction allows the status register to be read. the instruction code of ?05h? is for status register-1 and ?35h? is for status register-2. the status register may be read at any time, even while a program, erase or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register continuously, as shown in figure 5. table 4-a status register-1 format srp0 sec bp2 bp1 bp0 wel wip status register protect 0 (non-volatile) block protect bits (non-volatile) write enable latch bit write in progress bit b0 b7 tb b6 b5 b4 b3 b2 b1 top/bottom bit (non-volatile) sector protect (non-volatile) table 4-b status register-2 format sus cmp 0 0 apt qe 0 all protect (auto write protect) reserved b8 b15 0 b14 b13 b12 b11 b10 b9 quad enable (non-volatile) reserved complement protect (non-volatile) suspend status (volatile) the status and control bits of the status register are as follows: wip bit. the write in progress (wip) bit is a read only bit in the status register (b0) that is set to a 1 state when the device is busy with a write status register, program or erase cycle. during this time the device will ignore further instructions except for the read status register, suspend and resume instructions (see t w , t pp , t se , t be , and t ce in ac characteristics). when the program, erase, write status register instruction has completed or program/erase suspend instruction is execut ed, the wip bit will be cleared to a 0 state indicating the device is ready for further instructions. wel bit. the write enable latch (wel) bit is a read only bit in the status register (b1) that is set to a 1 after executing a write enable instruction. the wel status bit is cleared to a 0 when the device is write disabled or program/erase suspended. a write disable state occurs upon power-up or after any of the following instructions: write disable, page program, dual input fast program, quad input fast program, sector erase, block erase, chip erase, and write status register. bp2, bp1, bp0 bits. the block protect (bp2, bp1, and bp0) bits are non-volatile read/write bits in the status register (b4, b3, and b2) that provide write protection control and status. block protect bits can be set using the write status register instruction (see t w in ac characteristics). all, none or a portion of the memory array can be protected from program and erase instructions (see table 1. protected area sizes). these bits can be set with the write status register instruction depending on the state of srp0 and wel bit. the factory default setting for the block protect bits is 0 which means none of the array protected. for value of bp2, bp1, bp0 after power-on, see note please. tb bit. the non-volatile top/bottom (tb) bit controls if the block protect bits (bp2, bp1, bp0) protect from the top (tb=0) or the bottom (tb=1) of the array as shown in table 1. protected area sizes. the factory default setting is tb=0. the tb bit can be set with the write status register instruction depending on the state of srp0 and wel bit. sec bit. the non-volatile sector protect (sec) bit in the status register (b6) controls if the block protect bits (bp2, bp1, bp0) protect 4kb sectors (sec=1) or 64kb blocks (sec=0) in the top (tb=0) or the bottom (tb=1) of the array as shown in table 1. protected area sizes. this bit can be set with the write status register instruction depending on the state of the srp0, and wel bit. the factory default setting for sec is 0. srp0 bit. the status register protect bit (srp0) is a non-volatile read/write bit in the status register (b7). the srp0 bit controls the method of write protection: software protection, hardware protecti on, or one time programmable protection. qe bit. the quad enable (qe) bit is a non-volatile read/write bit in the status register (b9) that allows quad spi operation. when qe is set to 0(factory default), the w pin and hold pin are enabled. when qe is set to 1, the w pin and hold pin become io 2 and io 3 . this bit can be set with the write status register instruction depending on the state of the srp0 and wel bit. the factory default setting for qe is 0. apt bit. the all protect (apt) bit is a non-volatile read/write bit in the status register (b10). whole chip will be kept in write-protect state after power-on if this bit is set to 1. this bit can be set with the write status register instruction depending on the state of srp0 and wel bit. the factory default setting for apt is 0. cmp bit. the complement protect (cmp) bit is a non-volatile read/write bit in the status register (b14). it?s used in conjunction with sec, tb, bp2, bp1, bp0 bits to provide more flexibility for the array protection. once cmp is set to 1, previous array protection set by sec, tb, bp2, bp1 and bp0 will be reversed. please refer to table 1 for more details. the factory default setting for cmp is 0.
a25lq080 series (april, 2016, version 1.0) 15 amic technology corp. sus bit. the suspend status (sus) bit is a volatile read only bit in the status register (b15) which is set to 1 after executing a program/erase suspend instruction. the sus bit is cleared to 0 by program/erase resume instruction as well as a power-down, power-up cycle. note : 1. when apt is 0, bp2, bp1, bp0 won?t be changed after power-on. 2. when apt is 1 and cmp is 0, all bp2, bp1, bp0 will be set to 1 after power-on. 3. when apt is 1 and cmp is 1, all bp2, bp1, bp0 will be set to 0 after power-on. figure 5. read status register (rdsr) instruction sequence and data-out sequence 0 1 2 3 4 5 6 7 810 91112 13 14 15 msb msb status register 1 or 2 out status register 1 or 2 out high impedance instruction (05h or 35h) 01234 5 6 7 0 1 2 3 4 5 6 77 s di do 16 17 18 19 20 21 22 23 c
a25lq080 series (april, 2016, version 1.0) 16 amic technology corp. write status register (wrsr) the write status register (wrsr) instruction allows new values to be written to the status register. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrsr) instruction is entered by driving chip select ( s ) low, followed by the instruction code and the data byte on serial data input (di). the instruction sequence is shown in figure 6. only non-volatile status register bits srp0, sec, tb, bp2, bp1, bp0 (bits 7, 6, 5, 4, 3, 2 of status register-1) and cmp, apt, qe (bits 14, 10 and 9 of status register-2) can be written. all other status register bits are always read as ?0? and will not be affected by the write status register instruction. chip select ( s ) must be driven high after the eighth or sixteenth bit of the data byte has been latched in. if not, the write status register (wrsr) instruction is not executed. if chip select ( s ) is driven high after the eighth clock the cmp and qe bits will be cleared to 0. as soon as chip select ( s ) is driven high, the self-timed write status register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch (wel) is reset. the write status register (wrsr) instruction allows the user to change the values of the block protect (apt, cmp, sec, tb, bp2, bp1, bp0) bits, to define the size of the area that is to be treated as read-only, as defined in table 1. the write status register (wrsr) instruction also allows the user to set the status register protect (srp0) bit. those bits are used in conjunction with the write protect ( w ) pin to disable writes to the status register. factory default for all status register bits are 0. figure 6. write status register (wrsr) instruction sequence 8 9 2 3 4 5 6 7 810 91112 13 14 15 msb high impedance instruction (01h) 012345 6 7 0 1 s 16 17 18 19 20 21 22 23 status register in c 15 14 13 12 11 10 di do table 5. protection modes srp0 w status register description 0 x software protection status register is writable (if the wren instruction has set the wel bit). the values in the cmp, apt, srp0, sec, tb, bp2, bp1, bp0 bits can be changed. 1 0 hardware protection status register is hardware write protected. the values in the cmp, apt, srp0, sec, tb, bp2, bp1, bp0 bits cannot be changed. 1 1 software protection when w pin is high. status register is writable (if the wren instruction has set the wel bit). the values in the cmp, apt, srp0, sec, tb, bp2, bp1, bp0 bits can be changed.
a25lq080 series (april, 2016, version 1.0) 17 amic technology corp. read data bytes (read) the device is first selected by driving chip select ( s ) low. the instruction code for the read data bytes (read) instruction is followed by a 3-byte address (a23-a0), each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on serial data output (do), each bit being shifted out, at a maximum frequency f r , during the falling ed ge of serial clock (c). the instruction sequence is shown in figure 7. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes (read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes (read) instruction is terminated by driving chip select ( s ) high. chip select ( s ) can be driven high at any time during data output. any read data bytes (read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 7. read data bytes (read) instruction sequence and data-out sequence s c di do instruction (03h) high impedance msb msb 810 9 012345 6 7 data out 1 data out 2 24-bit address 28 29 30 31 32 33 34 35 36 37 38 39 23 22 21 3 210 7 6 54 32 10 7 note: address bits a23 to a20 are don?t care, for a25lq080.
a25lq080 series (april, 2016, version 1.0) 18 amic technology corp. read data bytes at higher speed (fast_read) the device is first selected by driving chip select ( s ) low. the instruction code for the read data bytes at higher speed (fast_read) instruction is followed by a 3-byte address (a23-a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on serial data output (do), each bit being shifted out, at a maximum frequency f c , during the falling edge of serial clock (c). the instruction sequence is shown in figure 8. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes at higher speed (fast_read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes at higher speed (fast_read) instruction is terminated by driving chip select ( s ) high. chip select ( s ) can be driven high at any time during data output. any read data bytes at higher speed (fast_read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 8. read data bytes at higher speed (fast_read) instruction sequence and data-out sequence instruction (0bh) high impedance msb 810 9 012345 6 7 24-bit address 28 29 30 31 23 22 21 3 210 data out 1 data out 2 7 0 s c di do s c di do 32 33 34 35 36 37 38 39 654 1 7 3 40 41 42 43 44 45 46 47 20 dummy byte msb 0 msb 7 6 54 32 1 msb 7 6 54 32 1 0 note: address bits a23 to a20 are don?t care, for a25lq080.
a25lq080 series (april, 2016, version 1.0) 19 amic technology corp. read data bytes at higher speed by dual output (fast_read_dual_output) the fast_read_dual_output (3bh) instruction is similar to the fast_read (0bh) instruction except the data is output on two pins, io 0 and io 1 , instead of just do. this allows data to be transferred from the a25lq080 at twice the rate of standard spi devices. similar to the fast_read instruction, the fast_read_dual_output instruction can operate at the highest possible frequency of f c (see ac characteristics). this is accomplished by adding eight ?dummy? clocks after the 24-bit address as shown in figure 9. the dummy clocks allow the device?s internal circuits additional time for setting up the initial address. the input data during the dummy clocks is ?don?t care?. however, the io 0 and io 1 pins should be high-impedance prior to the falling edge of the first data out clock. figure 9. fast_read_dual_output instruction sequence and data-out sequence instruction (3bh) high impedance msb 810 9 012345 6 7 24-bit address 28 29 30 31 23 22 21 3 210 7 0 s c io 0 s c 32 33 34 35 36 37 38 39 654 1 7 3 40 41 42 43 44 45 46 47 20 dummy byte msb 1 msb 7 5 31 75 3 msb 7 5 31 75 3 1 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 data out 1 data out 2 data out 3 data out 4 dio switches from input to output io 1 io 0 io 1 note: address bits a23 to a20 are don?t care, for a25lq080.
a25lq080 series (april, 2016, version 1.0) 20 amic technology corp. read data bytes at higher speed by dual input and dual output (fast_read_dual_input_output) the fast_read_dual_input_output (bbh) instruction is similar to the fast_read (0bh) instruction except the data is input and output on two pins, io 0 and io 1 , instead of just do. this allows data to be transferred from the a25lq080 at twice the rate of standard spi devices. similar to the fast_read instruction, the fast_read_dual_input_output instruction can operate at the highest possible frequency of f c (see ac characteristics). figure 10. fast_read_dual_input_output instruction sequence and data-out sequence instruction (bbh) high impedance msb 810 9 012345 6 7 24-bit address 16 17 18 19 22 20 18 6 420 7 0 s c io 0 io 1 s c 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 dummy byte msb 1 msb 7 5 31 75 3 msb 7 5 31 75 3 1 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 data out 2 data out 3 data out 4 data out 5 dio switches from input to output 21 19 5 3 1 23 7 6 4 2 0 6 4 2 0 7 531 msb data out 1 io 0 io 1 7 5 3 1 note: address bits a23 to a20 are don?t care, for a25lq080.
a25lq080 series (april, 2016, version 1.0) 21 amic technology corp. read data bytes at higher speed by quad output (fast_read_quad_output) the fast_read_quad_output (6bh) instruction is similar to the fast_read (0bh) instruction except the data is output on four pins (io 0 , io 1 , io 2 , io 3) , instead of just do. this allows data to be transferred from the a25lq080 at quadruple the rate of standard spi devices. similar to the fast_read instruction, the fast_read_quad_output instruction can operate at the highest possible frequency of f c (see ac characteristics). this is accomplished by adding eight ?dummy? clocks after the 24-bit address as shown in figure 11. the dummy clocks allow the device?s internal circuits additional time for setting up the initial address. the input data during the dummy clocks is ?don?t care?. howe ver, the io pins should be high-impedance prior to the falling edge of the first data out clock. figure 11. fast_read_quad_output instru ction sequence and data-out sequence instruction (6bh) high impedance msb 810 9 012345 6 7 24-bit address 28 29 30 31 23 22 21 3 210 5 0 s c io 0 s c 32 33 34 35 36 37 38 39 654 1 7 3 40 41 42 43 44 45 46 47 20 dummy byte 1 5 1 51 51 5 4 0 4 0 4 0 4 0 io switches from input to output io 1,2,3 io 0 io 1 6 2 6 2 62 62 6 io 2 7 3 7 3 73 73 7 data out 1data out 2data out 3data out 4 io 3 4 note: address bits a23 to a20 are don?t care, for a25lq080.
a25lq080 series (april, 2016, version 1.0) 22 amic technology corp. read data bytes at higher speed by quad input and quad output (fast_read_quad_input_output) the fast_read_quad_input_output (ebh) instruction is similar to t he fast_read (0bh) instruction except the data is input and output on four pins (io 3 , io 2 , io 1 , io 0 ) instead of just do. this allows data to be transferred from the a25lq080 at quadruple the rate of standard spi devices. the quad enable bit (qe) of status register-2 must be set to enable the fast_read_quad_input_output instruction. similar to the fast_read instruction, the fast_read_quad_input_output instruction can operate at the highest possible frequency of f c (see ac characteristics). figure 12. fast_read_quad_input_outpu t instruction and data-out sequence instruction (ebh) 810 9 01 234 5 6 7 20 16 12 8 40 4 s c io 0 io 1 11 12 13 14 15 16 17 18 19 20 21 22 23 4 04 0 21 17 13 9 51 5 5 15 1 22 18 14 10 62 6 6 26 2 23 19 15 11 73 7 7 37 3 a23-16 a15-8 a7-0 dummy dummy dummy data out 1 data out 2 io switches from input to output io 2 io 3 note: address bits a23 to a20 are don?t care, for a25lq080.
a25lq080 series (april, 2016, version 1.0) 23 amic technology corp. read otp (rotp) the device is first selected by driving chip select ( s ) low. the instruction code for the read otp (rotp) instruction is followed by a 3-byte address (a23- a0) and a dummy byte. each bit is latched in on the rising edge of serial clock (c). then the memory contents at that address are shifted out on serial data output (do). each bit is shifted out at the maximum frequency, f c (max.) on the falling edge of serial clock (c). the instruction sequence is shown in figure 13. the address is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read otp (rotp) instruction is terminated by driving chip select ( s ) high. chip select ( s ) can be driven high at any time during data output. any read otp (rotp) instruction issued while an erase, program or write status register cycle is in progress, is rejected without having any effect on the cycle that is in progress. figure 13. read otp (rotp) instruction and data-out sequence instruction (4bh or 48h) high impedance msb 810 9 01 234 5 6 7 24-bit address 28 29 30 31 23 22 21 3 210 7 0 s c s c 32 33 34 35 36 37 38 39 654 1 7 3 40 41 42 43 44 45 46 47 20 dummy byte msb msb 7 6 54 32 1 msb 7 6 54 32 1 0 data out 1 data out n 0 di do di do note: a23 to a6 are don?t care. (1 n 64)
a25lq080 series (april, 2016, version 1.0) 24 amic technology corp. program otp (potp) the program otp instruction (potp) is used to program at most 64 bytes to the otp memory area (by changing bits from 1 to 0, only). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel) bit. the program otp instruction is entered by driving chip select ( s ) low, followed by the instruction code, three address bytes and at least one data byte on serial data input (di). chip select ( s ) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the program otp instruction is not executed. the instruction sequence is shown in figure 14. as soon as chip select ( s ) is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the program otp cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed program otp cycle, and it is 0 when it is completed. at some unspecified time before the cycle is complete, the write enable latch (wel) bit is reset. to lock the otp memory: bit 0 of the otp control byte, that is byte 63, (see figure 14) is used to permanently lock the otp memory array. ? when bit 0 of byte 63 = ?1?, the otp memory array can be programmed. ? when bit 0 of byte 63 = ?0?, the otp memory array are read-only and cannot be programmed anymore. once a bit of the otp memory has been programmed to ?0?, it can no longer be set to ?1?. therefore, as soon as bit 0 of address 63h (control byte) is set to ?0?, the 64 bytes of the otp memory array become read-only in a permanent way. any program otp (potp) instruction issued while an erase, program or write status register cycle is in progress is rejected without having any effect on the cycle that is in progress. figure 14. program otp (potp) instruction sequence instruction (42h) msb 810 9 01 234 5 6 7 24-bit address 28 29 30 31 23 22 21 3 210 7 0 s c di s c di 40 41 42 43 44 45 46 47 654 1 7 3 48 49 50 51 52 53 54 55 20 data byte 2 msb msb 7 6 54 32 1 msb 7 6 54 32 1 0 0 32 33 34 35 36 37 38 39 data byte 1 650 4 210 0 73 msb data byte 3 data byte n note: a23 to a6 are don?t care. (1 n 64)
a25lq080 series (april, 2016, version 1.0) 25 amic technology corp. figure 15. how to permanently lock the 64 otp bytes otp control byte 64 data byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 when bit 0 =0 the otp bytes become read only byte 0 byte 1 byte 2 byte 62 byte 63
a25lq080 series (april, 2016, version 1.0) 26 amic technology corp. page program (pp) the page program (pp) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page program (pp) instruction is entered by driving chip select ( s ) low, followed by the instruction code, three address bytes and at least one data byte on serial data input (di). if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (a7-a0) are all zero). chip select ( s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 16. if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. chip select ( s ) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the page program (pp) instruction is not executed. as soon as chip select ( s ) is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a page program (pp) instruction applied to a page which is protected by the block protect (cmp, sec, tb, bp2, bp1, bp0) bits (see table 1) is not executed. figure 16. page program (pp) instruction sequence s c di instruction (02h) msb 810 9 012345 6 7 24-bit address 28 29 30 31 32 33 34 35 36 37 38 39 23 22 21 3 210 data byte 1 msb 7 6 54 32 1 0 3 data byte 256 55 53 54 52 data byte 3 51 50 49 48 47 46 45 44 43 42 41 40 data byte 2 0 msb 7 6 54 32 1 msb 7 6 54 32 1 0 msb 7 6 54 32 1 0 s c di 2072 2073 2074 2075 2076 2077 2078 2079 note: address bits a23 to a20 are don?t care, for a25lq080.
a25lq080 series (april, 2016, version 1.0) 27 amic technology corp. dual input fast program (difp) the dual input fast program (difp) instruction is very similar to the page program (pp) instruction, except that the data are entered on two pins io 0 and io 1 instead of only one. inputting the data on two pins instead of one doubles the data transfer bandwidth compared to the page program (pp) instruction. the dual input fast program (difp) instruction is entered by driving chip select ( s ) low, followed by the instruction code, three address bytes and at least one data byte on serial data output (io 0 and io 1 ). if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (a7-a0) are all zero). chip select ( s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 17. if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes in the same page. for optimized timings, it is recommended to use the dual input fast program (difp) instruction to program all consecutive targeted bytes in a single sequence rather to using several dual input fast program (difp) sequences each containing only a few bytes. chip select ( s ) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the dual input fast program (difp) instruction is not executed. as soon as chip select ( s ) is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the dual input fast program (difp) cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page program cycle, and 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a dual input fast program (difp) instruction applied to a page that is protected by the block protect (cmp, sec, tb, bp2, bp1, bp0) bits (see table 1) is not executed. figure 17. dual input fast program (difp) instruction sequence instruction (a2h) high impedance msb 810 9 012345 6 7 24-bit address 28 29 30 31 23 22 21 3 210 0 s c io 0 io 1 s c io 0 io 1 32 33 34 35 36 37 38 39 420 2 6 6 40 41 42 43 44 45 46 47 40 msb msb msb 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 531 3 75 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 msb msb msb data in 1 data in 2 data in 3 data in 4 data in 5 data in 256 note: address bits a23 to a20 are don?t care, for a25lq080.
a25lq080 series (april, 2016, version 1.0) 28 amic technology corp. quad input fast program (qifp) the quad input fast program (qifp) instruction is very similar to the page program (pp) instruction, except that the data are entered on four pins (io 3 , io 2 , io 1 , io 0 ) instead of only one. inputting the data on four pins instead of one quadruples the data transfer bandwidth compared to the page program (pp) instruction. to use quad input fast program the quad enable bit (qe) of status register-2 must be set. the quad input fast program (qifp) instruction is entered by driving chip select ( s ) low, followed by the instruction code, three address bytes and at least one data byte on data input output (io 3 , io 2 , io 1 , io 0 ). if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (a7-a0) are all zero). chip select ( s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 18. if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes in the same page. for optimized timings, it is recommended to use the quad input fast program (qifp) instruction to program all consecutive targeted bytes in a single sequence rather to using several quad input fast program (qifp) sequences each containing only a few bytes. chip select ( s ) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the quad input fast program (qifp) instruction is not executed. as soon as chip select ( s ) is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the quad input fast program (qifp) cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page program cycle, and 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a quad input fast program (qifp) instruction applied to a page that is protected by the block protect (cmp, sec, tb, bp2, bp1, bp0) bits (see table 1) is not executed. figure 18. quad input fast program (qifp) instruction sequence s c io 0 instruction (32h) msb 810 9 01 234 5 6 7 24-bit address 28 29 30 31 32 33 34 35 36 37 38 39 23 22 21 3 210 4 0 40 40 4 0 3 55 53 54 52 51 50 49 48 47 46 45 44 43 42 41 40 s c io 0 536 537 538 539 540 541 542 543 byte 1 byte 2 byte 3 byte 4 5 1 51 51 51 6 2 62 62 62 7 3 73 73 73 msb io 1 io 2 io 3 1 5 1 51 51 5 5 1 51 51 5 1 5 1 51 51 5 1 2 6 2 62 62 6 6 2 62 62 6 2 6 2 62 62 6 2 3 7 3 73 73 7 7 3 73 73 7 3 7 3 73 73 7 3 0 4 0 40 40 4 4 0 40 40 4 0 4 0 40 40 4 0 byte 5 byte 6 byte 7 byte 8 byte 9 byte 10byte 11 byte 12 byte 253 byte 254byte 255 byte 256 io 1 io 2 io 3 note: address bits a23 to a20 are don?t care, for a25lq080
a25lq080 series (april, 2016, version 1.0) 29 amic technology corp. sector erase (se) the sector erase (se) instruction sets to 1 (ffh) all bits inside the chosen sector. before it can be accepted, a write enable (wren) instruction must previously have been ex- ecuted. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the sector erase (se) instruction is entered by driving chip select ( s ) low, followed by the instructio n code on serial data input (di). chip select ( s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 19. chip select ( s ) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the sector erase instruction is not executed. as soon as chip select ( s ) is driven high, the self-timed sector erase cycle (whose duration is t se ) is initiated. while the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a sector erase (se) instruction applied to a page which is protected by the block protect (cmp, sec, tb, bp2, bp1, bp0) bits (see table 1) is not executed. figure 19. sector erase (se) instruction sequence instruction (20h) msb 810 9 01234 5 6 7 24-bit address 28 29 30 31 23 s c di 22 21 3 210 0 23 note: address bits a23 to a20 are don?t care, for a25lq080.
a25lq080 series (april, 2016, version 1.0) 30 amic technology corp. block erase (be) the block erase (be) instruction sets to 1 (ffh) all bits inside the chosen block. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the block erase (be) instruction is entered by driving chip select ( s ) low, followed by the instructio n code on serial data input (di). chip select ( s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 20. chip select ( s ) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the block erase instruction is not executed. as soon as chip select ( s ) is driven high, the self-timed block erase cycle (whose duration is t be ) is initiated. while the block erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed block erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a block erase (be) instruction applied to a page which is protected by the block protect (cmp, sec, tb, bp2, bp1, bp0) bits (see table 1) is not executed. figure 20. block erase (be) instruction sequence instruction (d8h or 52h) msb 810 9 01234 5 6 7 24-bit address 28 29 30 31 23 s c di 22 21 3 210 0 23 note: address bits a23 to a20 are don?t care, for a25lq080.
a25lq080 series (april, 2016, version 1.0) 31 amic technology corp. chip erase (ce) the chip erase (ce) instruction sets all bits to 1 (ffh). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the chip erase (ce) instruction is entered by driving chip select ( s ) low, followed by the instruction code on serial data input (di). chip select ( s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 21. chip select ( s ) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the chip erase instruction is not executed. as soon as chip select ( s ) is driven high, the self-timed chip erase cycle (whose duration is t ce ) is initiated. while the chip erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed chip erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. the chip erase (ce) instruction is ignored if one, or more, sectors/blocks ar e protected. figure 21. chip erase (ce) instruction sequence s c di 1 2 3 4567 0 instruction (c7h or 60h)
a25lq080 series (april, 2016, version 1.0) 32 amic technology corp. deep power-down (dp) executing the deep power-down (dp) instruction is the only way to put the device in the lowest consumption mode (the deep power-down mode). it can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all write, program and erase instructions. driving chip select ( s ) high deselects the device, and puts the device in the standby mode (if there is no internal cycle currently in progress). but this mode is not the deep power-down mode. the deep power-down mode can only be entered by executing the deep power-down (dp) instruction, to reduce the standby current (from i cc1 to i cc2 , as specified in dc characteristics table.). once the device has entered the deep power-down mode, all instructions are ignored except the release from deep power-down and read electronic signature (res) instruction. this releases the device from this mode. the release from deep power-down and read electronic signature (res) instruction also allows the electronic signature of the device to be output on serial data output (do). the deep power-down mode automatically stops at power-down, and the device always powers-up in the standby mode. the deep power-down (dp) instruction is entered by driving chip select ( s ) low, followed by the instruction code on serial data input (di). chip select ( s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 22. chip select ( s ) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the deep power-down (dp) instruction is not executed. as soon as chip select ( s ) is driven high, it requires a delay of t dp before the supply current is reduced to i cc2 and the deep power-down mode is entered. any deep power-down (dp) instruction, while an erase, program or write status regist er cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 22. deep power-down (dp) instruction sequence s c di 1 2 3 4567 0 instruction (b9h) t dp stand-by mode deep power-down mode
a25lq080 series (april, 2016, version 1.0) 33 amic technology corp. read device identification (rdid) the read identification (rdid) instruction allows the 8-bit manufacturer identification code to be read, followed by two bytes of device identification. the manufacturer identification is assigned by jedec, and has the value 37h. the device identification is assigned by the device manufacturer, and indicates the memory in the first byte (40h), and the memory capacity of the device in the second byte (14h for a25lq080). any read identification (rdid) instruction while an erase, or program cycle is in progres s, is not decoded, and has no effect on the cycle that is in progress. the device is first selected by driving chip select ( s ) low. then, the 8-bit instruction code for the instruction is shifted in. this is followed by the 24-bit device identification, stored in the memory, being shifted out on serial data output (do), each bit being shifted out during the falling edge of serial clock (c). the instruction sequence is shown in figure 23. the read identification (rdid) instruction is terminated by driving chip select ( s ) high at any time during data output. when chip select ( s ) is driven high, the device is put in the stand-by power mode. once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. table 6. read identification (read_id) data-out sequence manufacture identification device identification manufacture id memory type memory capacity 37h 40h 14h (a25lq080) figure 23. read identification (rdid) instruction sequence and data-out sequence s c io 0 io 1 instruction (9fh) high impedance 810 9 01 2 3 4 5 6 7 21 30 22 23 24 25 26 29 31 manufacture id memory type 76 5 210 15 14 13 10 9 8 23 22 21 18 17 16 13 15 14 16 17 18 memory capacity
a25lq080 series (april, 2016, version 1.0) 34 amic technology corp. read electronic manufacturer id & device id (rems) the read electronic manufacturer id & device id (rems) instruction allows the 8-bit manufacturer identification code to be read, followed by one byte of device identification. the manufacturer identification is assigned by jedec, and has the value 37h for amic. the device identification is assigned by the device manufacturer, and has the value 13h for a25lq080. any read electronic manufacturer id & device id (rems) instruction while an erase, or program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the device is first selected by driving chip select ( s ) low. the 8-bit instruction code is followed by 2 dummy bytes and one byte address (a7~a0), each bit being latched-in on serial data input (di) during the rising edge of serial clock (c). if the one-byte address is set to 01h, then the device id will be read first and then followed by the manufacturer id. on the other hand, if the one-byte address is set to 00h, then the manufacturer id will be read first and then followed by the device id. the instruction sequence is shown in figure 24. the read electronic manufacturer id & device id (rems) instruction is terminated by driving chip select ( s ) high at any time during data output. when chip select ( s ) is driven high, the device is put in the stand-by power mode. once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. table 7. read electronic manufacturer id & device id (rems) data-out sequence manufacture identification device identification 37h 13h (a25lq080) figure 24. read electronic manufacturer id & device id (rems) instruction sequence and data-out sequence instruction (90h) high impedance msb 810 9 012345 6 7 2 dummy bytes 20 21 22 23 15 14 13 3 210 manufacturer id 0 s c di do s c di do 24 25 26 27 28 29 30 31 654 1 7 3 32 33 34 35 36 37 38 39 20 add (1) msb 0 msb 7 6 54 32 1 msb 7 6 54 32 1 0 40 41 42 43 44 45 46 47 device id notes: (1) add=00h will output the manufacturer id first and add=01h will output device id first
a25lq080 series (april, 2016, version 1.0) 35 amic technology corp. release from deep power-down and read electronic signature (res) once the device has entered the deep power-down mode, all instructions are ignored ex cept the release from deep power-down and read electronic signature (res) instruction. executing this instruction takes the device out of the deep power-down mode. the instruction can also be used to read, on serial data output (do), the 8-bit electronic signature, whose value for a25lq080 is 13h. except while an erase, program or write status register cycle is in progress, the release from deep power-down and read electronic signature (res) instruction always provides access to the 8-bit electronic signature of the device, and can be applied even if the deep power-down mode has not been entered. any release from deep power-down and read electronic signature (res) instruction while an erase, program or write status register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the device is first selected by driving chip select ( s ) low. the instruction code is followed by 3 dummy bytes, each bit being latched-in on serial data input (di) during the rising edge of serial clock (c). then, the 8-bit electronic signature, stored in the memory, is shifted out on serial data output (do), each bit being shifted out during the falling edge of serial clock (c). the instruction sequence is shown in figure 25. the release from deep power-down and read electronic signature (res) instruction is terminated by driving chip select ( s ) high after the electronic signature has been read at least once. sending additional clock cycles on serial clock (c), while chip select ( s ) is driven low, cause the electronic signature to be output repeatedly. when chip select ( s ) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the stand- by power mode is delayed by t res2 , and chip select ( s ) must remain high for at least t res2 (max), as specified in ac characteristics table . once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. figure 25. release from deep power-down and read electronic signature (res) instruction sequence and data-out sequence s c di do instruction (abh) high impedance msb msb 810 9 012345 6 7 3 dummy bytes 28 29 30 31 32 33 34 35 36 37 38 23 22 21 3 210 6 54 32 10 7 t res2 stand-by mode deep power-down mode note: the value of the 8-bit electronic signature, for a25lq080 is 13h.
a25lq080 series (april, 2016, version 1.0) 36 amic technology corp. figure 26. release from deep power-down (res) instruction sequence s c di 1 2 3 4567 0 instruction (abh) t res1 high impedance do stand-by mode deep power-down mode driving chip select ( s ) high after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit electronic signature has been transmitted for the first time (as shown in figure 26.), still insures that the device is put into stand-by power mode. if the device was not pre- viously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the stand-by power mode is delayed by t res1 , and chip select ( s ) must remain high for at least t res1 (max), as specified in ac characteristics table. once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
a25lq080 series (april, 2016, version 1.0) 37 amic technology corp. high performance mode (a3h) the high performance mode (hpm) instruction can be executed prior to dual or quad i/o instructions if chip is operated at high frequencies. this instruction allows pre-charging of internal charge pumps so the voltages required for accessing the flash memory array are readily available. the instruction sequence includes the a3h instruction code followed by three dummy byte clocks shown in fig.28. after the hpm instruction is executed, the device will maintain a slightly higher standby current than standard spi operation. the release from power-down (abh) can be used to return to standard spi standby current (i cc1 ). in addition, write enable instruction (06h) and power down instruction (b9h) will also release the device from hpm mode back to standard spi standby state. figure 27. high performance mode instruction sequence instruction (a3) msb 810 9 012345 6 7 3 dummy bytes 28 29 30 31 23 22 21 3 210 0 s c t res2 high performance current di do
a25lq080 series (april, 2016, version 1.0) 38 amic technology corp. program / erase suspend the suspend instruction allows the system to interrupt a sector or block erase operation or a page program operation and then read from or program data to, any other sectors or blocks. the suspen d instruction sequence is shown in figure 29. the write status register instruction (01h) and erase instructions (20h, 52h, d8h, c7h, 60h) are not allowed during erase suspend. erase suspend is valid only during the sector or block erase operation. if written during the chip erase operation, the erase suspend instruction is ignored. the write status register instruction (01h) and page program instructions (02h) ar e not allowed during program suspend. program suspend is valid only during the page program operation. the suspend instruction will be accepted by the device only if the sus bit in the status register equals to 0 and the wip bit equals to 1 while a sector or block erase or a page program operation is on-going. if the sus bit equals to 1 or the busy bit equals to 0, the suspend instruction will be ignored by the device. a maximum of time of ?t sus ? (see ac characteristics) is required to suspend the erase or program operation. the wip bit in the status register will be cleared from 1 to 0 within ?t sus ? and the sus bit in the status register will be set from 0 to 1 immediately after program/erase suspend. for a previously resumed program/erase operation, it is also required that the suspend instruction is not issued earlier than a minimum of time of ?t sus ? following the preceding resume instruction. unexpected power off during the program/erase suspend state will reset the device and release the suspend state. sus bit in the status register will also reset to 0. the data within the page, sector or block that was being suspended may become corrupted. it is recommended for the user to implement system design techniques against the accidental power interruption and preserve data integrity during program/erase suspend state. figure 28. suspend instruction sequence s c dio 1 2 3 4567 0 instruction (75h or b0h) accept read or program instruction high impedance t sus do table 8. operations allowed and not allowed during a program or erase suspend command operation during program suspend operation during erase suspend read commands read data allowed allowed program and erase commands pp not allowed allowed se/ be/ ce not allowed not allowed status register commands rdsr-1/ rdsr-2 allowed allowed wrsr not allowed not allowed other commands suspend not allowed not allowed resume allowed allowed hpm allowed allowed wren allowed allowed wrdi allowed allowed rdid/ rems/ res/ sfdp allowed allowed dp not allowed not allowed
a25lq080 series (april, 2016, version 1.0) 39 amic technology corp. program / erase resume the resume instruction must be written to resume the sector or block erase operation or the page program operation after a program/erase suspend. the resume instruction will be accepted by the device only if the sus bit in the status register equals to 1 and the wip bit equals to 0. after issued the sus bit will be cleared from 1 to 0 immediately, the wip bit will be set from 0 to 1 within 200ns and the sector or block will complete the erase operation or the page will complete the program operation. if the sus bit equals to 0 or the wip bit equals to 1, the resume instruction will be ignored by the device. the resume instruction sequence is shown in figure 30. resume instruction is ignored if the previous program/erase suspend operation was interrupted by unexpected power off. it is also required that a subsequent program/erase suspend instruction not to be issued within a minimum of time of ?t sus ? following a previous resume instruction. figure 29. resume instruction sequence s c dio 1 2 3 4567 0 instruction (7ah or 30h) resume sector or block erase high impedance do
a25lq080 series (april, 2016, version 1.0) 40 amic technology corp. read sfdp register (5ah) the a25lq080 features a 64-byte serial flash discoverable parameter (sfdp) register that contains information about devices operational capability such as available commands, timing and other features. the sfdp parameters are stored in one or more parameter identification (pid) tables. currently only one pid table is specified but more may be added in the future. the read sfdp register instruction is compatible with the jedec sfdp standard (jesd216) established in 2011. the read sfdp instruction is initiated by driving chip select ( s ) low and shifting the instruction code ?5ah? followed by a 24-bit address (a23-a0) (1) into the dio pin. eight ?dummy? clocks are also required before the sfdp regist er contents are shifted out on the falling edge of the 40 th serial clock (c) with most significant bit (msb) first as shown in figure 31. for sfdp register values and descriptions, refer to the following sfdp definition table. note: 1. a23-a6 = 0; a5-a0 are used to define the starting byte address for the 64-byte sfdp register. figure 30. read sfdp register instruction sequence diagram instruction (5ah) high impedance 810 9 012345 6 7 24-bit address 28 29 30 31 23 22 21 3 210 data out 1 data out 2 7 0 s c dio do s c dio do 32 33 34 35 36 37 38 39 654 1 7 3 40 41 42 43 44 45 46 47 20 dummy byte msb 0 msb 7 6 54 32 1 msb 7 6 54 32 1 0
a25lq080 series (april, 2016, version 1.0) 41 amic technology corp. table 9. sfdp definition table description address(h) (byte mode) address (bit) data comment 00h 7:0 53h 01h 15:8 46h 02h 23:16 44h spi flash discoverability parameters (sfdp) signature 03h 31:24 50h hex: 50444653 minor revision 04h 7:0 00h start from 0x00 sfdp revision major revision 05h 15:8 01h start from 0x01 number of parameter header 06h 23:16 00h reserved 07h 31:24 ffh reserved parameter id(0) 08h 7:0 00h parameter minor revision 09h 15:8 00h start from 0x00 parameter major revision 0ah 23:16 01h start from 0x01 parameter length (in dw) 0bh 31:24 09h parameter table pointer 0eh:0ch 23:00 000010h reserved 0fh 31:24 ffh reserved
a25lq080 series (april, 2016, version 1.0) 42 amic technology corp. parameter id (0) description address(h) (byte mode) address (bit) data comment block/sector erase sizes 01:00 01 00= reserved 01=4kb erase 10= reserved 11=64kb erase write granularity 02 1 0=1byte 1=64byte write enable command required for writing to volatile status register 03 0 write enable opcode select for writing to volatile status register 04 0 unused 10h 07:05 7h reserved 4kilo byte erase opcode 11h 15:08 20h 4kb erase support (ffh=not supported) supports single input address dual output fast read 16 1 0=not supported 1=support number of bytes used in addressing for flash array read, write and erase 18:17 00 00=3 byte 01=3 byte or 4byte 10= 4-byte only 11= reserved supports dual transfer rate clocking 19 0 0=not supported 1=support supports dual input address dual output fast read 20 1 0=not supported 1=support supports quad input address quad output fast read 21 1 0=not supported 1=support supports single input address quad output fast read 22 1 0=not supported 1=support 12h 23 1 unused 13h 31:24 ffh reserved flash size in bits 17h to 14h 31:00 007fffffh 8mb
a25lq080 series (april, 2016, version 1.0) 43 amic technology corp. parameter id (0) (continued) description address(h) (byte mode) address (bit) data comment quad input address quad output fast read number of wait states(dummy bits) needed before valid output 04:00 00110 quad input address quad output fast read number of mode bits 18h 07:05 000 this filed should be counted in clocks. quad input address quad output fast read opcode 19h 15:08 ebh single input address quad output fast read number of wait states(dummy bits) needed before valid output 20:16 01000 single input address quad output fast read number of mode bits 1ah 23:21 000 this filed should be counted in clocks. single input address quad output fast read opcode 1bh 31:24 6bh single input address dual output fast read number of wait states(dummy bits) needed before valid output 04:00 01000 single input address dual output fast read number of mode bits 1ch 07:05 000 this filed should be counted in clocks. single input address dual output fast read opcode 1dh 15:08 3bh dual input address dual output fast read number of wait states(dummy bits) needed before valid output 20:16 00100 dual input address dual output fast read number of mode bits 1eh 23:21 000 this filed should be counted in clocks. dual input address dual output fast read opcode 1fh 31:24 bbh
a25lq080 series (april, 2016, version 1.0) 44 amic technology corp. parameter id (0) (continued) description address(h) (byte mode) address (bit) data comment supports (2-2-2) fast read 0 0 not supported reserved 03:01 7h supports (4-4-4) fast read 04 0 not supported reserved 20h 07:05 7h reserved 23h to 21h 31:08 ffffffh reserved 25h to 24h 15:0 ffffh (2-2-2) fast read number of wait states 20:16 00000 (2-2-2) fast read number of mode bits 26h 23:21 000 (2-2-2) fast read opcode 27h 31:24 00h not supported reserved 29h to 28h 15:0 ffffh (4-4-4) fast read number of wait states 20:16 00000 (4-4-4) fast read number of mode bits 2ah 23:21 000 (4-4-4) fast read opcode 2bh 31:24 00h not supported sector type 1 size (4kb) 2ch 07:00 0ch sector type 1 opcode 2dh 15:08 20h sector type 2 size (32kb) 2eh 23:16 00h sector type 2 opcode 2fh 31:24 00h not supported sector type 3 size (64kb) 30h 07:00 10h sector type 3 opcode 31h 15:08 d8h sector type 4 size (256kb) 32h 23:16 00h sector type 4 opcode 33h 31:24 00h not supported notes: 1. data stored in byte address 34h to 3fh are reserved, the value is ffh.
a25lq080 series (april, 2016, version 1.0) 45 amic technology corp. power-up and power-down at power-up and power-down, the device must not be selected (that is chip select ( s ) must follow the voltage applied on v cc ) until v cc reaches the correct value: - v cc (min) at power-up, and then for a further delay of t vsl - v ss at power-down usually a simple pull-up resistor on chip select ( s ) can be used to insure safe and proper power-up and power-down. to avoid data corruption and inadvertent write operations during power up, a power on reset (por) circuit is included. the logic inside the device is held reset while v cc is less than the por threshold value, v wi ? all operations are disabled, and the device does not respond to any instruction. moreover, the device ignores all write enable (wren), program otp (potp), page program (pp), dual input fast program (difp), quad input fast program (qifp), sector erase (se), block erase (be) , chip erase (ce) and write status register (wrsr) instructions until a time delay of t puw has elapsed after the moment that v cc rises above the v wi threshold. however, the correct operation of the device is not guaranteed if, by this time, v cc is still below v cc (min). no write status register, program or erase instructions should be sent until the later of: - t puw after v cc passed the v wi threshold - t vsl afterv cc passed the v cc (min) level these values are specified in table 9. if the delay, t vsl , has elapsed, after v cc has risen above v cc (min), the device can be selected for read instructions even if the t puw delay is not yet fully elapsed. at power-up, the device is in the following state: - the device is in the standby mode (not the deep power-down mode). - the write enable latch (wel) bit is reset. normal precautions must be taken for supply rail decoupling, to stabilize the v cc feed. each device in a system should have the v cc rail decoupled by a suitable capacitor close to the package pins. (generally, this capacitor is of the order of 0.1f). at power-down, when v cc drops from the operating voltage, to below the por threshold value, v wi , all operations are disabled and the device does not respond to any instruction. (the designer needs to be aware that if a power-down occurs while a write, program or erase cycle is in progress, some data corruption can result.) figure 31. power-up timing time v cc v cc (max) v cc (min) t puw full device access v wi t vsl read access allowed reset state
a25lq080 series (april, 2016, version 1.0) 46 amic technology corp. table 9. power-up timing symbol parameter min. max. unit t vsl v cc(min) to s low 10 s t puw time delay before write instruction 3 ms v wi write inhibit threshold voltage 2.3 2.5 v note: these parameters are characterized only. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register conta ins 00h (all status register bits are 0).
a25lq080 series (april, 2016, version 1.0) 47 amic technology corp. absolute maximum ratings* storage temperature (tstg) . . . . . . . . . . -65 c to + 150 c lead temperature during soldering (note 1) d.c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6v to v cc +0.6v transient voltage (<20ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v cc +2.0v supply voltage (v cc ) . . . . . . . . . . . . . . . . . . -0.6v to +4.0v electrostatic discharge voltage (human body model) (vesd) (note 2) . . . . . . . . . . . . . . . . . . . -2000v to 2000v notes: 1. compliant with jedec std j-std-020b (for small body, sn-pb or pb assembly). 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 , r2=500 ) *comments stressing the device above the rating listed in the absolute maximum ratings" table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the amic sure program and other relevant quality documents. dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. table 10. operating conditions symbol parameter min. max. unit v cc supply voltage 2.7 3.6 v t a ambient operating temperature ?40 85 c table 11. data retention and endurance parameter condition min. max. unit erase/program cycles at 85c 100,000 cycles data retention at 85c 20 years table 12. capacitance symbol parameter test condition min. max. unit c out output capacitance (do) v out = 0v 8 pf c in input capacitance (other pins) v in = 0v 6 pf note: sampled only, not 100% tested, at t a =25 c and a frequency of 33 mhz.
a25lq080 series (april, 2016, version 1.0) 48 amic technology corp. table 13. dc characteristics symbol parameter test condition min. max. unit i li input leakage current 2 a i lo output leakage current 2 a i cc1 standby current s = v cc , v in = v ss or v cc 1 15 a i cc2 deep power-down current s = v cc , v in = v ss or v cc 1 15 a c= 0.1v cc / 0.9.v cc at 100mhz, do = open 24 ma c= 0.1v cc / 0.9.v cc at 50mhz, do = open 21 ma operating current (read) c= 0.1v cc / 0.9.v cc at 33mhz, do = open 17 ma operating current (dual read) c= 0.1v cc / 0.9.v cc at 100mhz, io 0 , io 1 = open 26 ma i cc3 operating current (quad read) c= 0.1v cc / 0.9.v cc at 100mhz, io 0 ~ io 3 = open 28 ma i cc4 operating current (pp) s = v cc 15 ma i cc5 operating current (wrsr) s = v cc 12 ma i cc6 operating current (se) s = v cc 25 ma i cc7 operating current (be) s = v cc 25 ma v il input low voltage ?0.5 0.3v cc v v ih input high voltage 0.7v cc v cc +0.4 v v ol output low voltage i ol = 1.6ma 0.4 v v oh output high voltage i oh = ?100a v cc ?0.2 v note: 1. this is preliminary data at 85c table 14. ac measurement conditions symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltages 0.2v cc to 0.8v cc v input timing reference voltages 0.3v cc to 0.7v cc v output timing reference voltages v cc / 2 v note: output hi-z is defined as the point where data out is no longer driven. figure 32. ac measurement i/o waveform 0.3v cc 0.5v cc 0.2v cc 0.7v cc 0.8v cc input levels input and output timing reference levels
a25lq080 series (april, 2016, version 1.0) 49 amic technology corp. table 15. ac characteristics symbol alt. parameter min. typ. max. unit f c f c clock frequency for all instructions, except read (03h) d.c. 100 mhz f r clock frequency for read (03h) instruction d.c. 50 mhz t ch 1 t clh clock high time 5 ns t cl 1 t cll clock low time 5 ns t clch 2 clock rise time 3 (peak to peak) 0.1 v/ns t chcl 2 clock fall time 3 (peak to peak) 0.1 v/ns t slch t css s active setup time (relative to c) 5 ns t chsl s not active hold time (relative to c) 5 ns t dvch t dsu data in setup time 3 ns t chdx t dh data in hold time 3 ns t chsh s active hold time (relative to c) 5 ns t shch s not active setup time (relative to c) 5 ns t shsl t csh s deselect time 30 ns t shqz 2 t dis output disable time 7 ns t clqv t v clock low to output valid 7 ns t clqx t ho output hold time 0 ns t hlch hold setup time (relative to c) 5 ns t chhh hold hold time (relative to c) 5 ns t hhch hold setup time (relative to c) 5 ns t chhl hold hold time (relative to c) 5 ns t hhqx 2 t lz hold to output low-z 7 ns t hlqz 2 t hz hold to output high-z 7 ns t whsl 4 write protect setup time 20 ns t shwl 4 write protect hold time 100 ns t dp 2 s high to deep power-down mode 3 s t res1 2 s high to standby mode without electronic signature read 1 s t res2 2 s high to standby mode with electronic signature read 1 s t w write status register cycle time 5 20 ms page program cycle time 2 6 ms t pp program otp cycle time 2 3 ms t se sector erase cycle time 0.08 0.2 s t be block erase cycle time 0.5 2 s t ce chip erase cycle time of a25lq080 8 20 s note: 1. t ch + t cl must be greater than or equal to 1/ f c 2. value guaranteed by characterization, not 100% tested in production. 3. expressed as a slew-rate. 4. only applicable as a constraint for wrsr instruction when status register protect bit (srp0) = 1
a25lq080 series (april, 2016, version 1.0) 50 amic technology corp. figure 33. serial input timing s c di tshsl high impedance do tslch tchsl tshch tchdx tchsh tdvch tclch lsb in msb in tchcl figure 34. write protect setup and hold timing during wrsr high impedance twhsl tshwl s c di do w
a25lq080 series (april, 2016, version 1.0) 51 amic technology corp. figure 35. hold timing s c do di hold thlqz thlch thhch tchhl tchhh thhqx figure 36. output timing s c do di addr.lsb in lsb out tclqv tclqv tch tclqx tclqx tcl tqlqh tqhql tshqz
a25lq080 series (april, 2016, version 1.0) 52 amic technology corp. part numbering scheme a25 xx package type blank = dip 8 m = 209 mil sop 8 o = 150 mil sop 8 q4 = wson 8 (6*5mm) device voltage l = 2.7-3.6v device type a25 = amic serial flash device density 080 = 8 mbit (4kb uniform sectors) x package material blank: normal f: pb free x x x quad spi operation q = support quad spi operation blank = do not sup port quad spi operation / x packing blank: for dip8 g: for sop8 in tube q: for tape & reel
a25lq080 series (april, 2016, version 1.0) 53 amic technology corp. ordering information part no. speed (mhz) active read current max. (ma) program/erase current max. (ma) standby current max. ( a) package a25lq080-f 8 pin pb-free dip (300 mil) a25lq080o-f 8 pin pb-free sop (150 mil) a25lq080m-f 8 pin pb-free sop (209mil) a25lq080q4-f 100 24 15 15 8 pin pb-free wson (6*5mm) operating temperature range: -40 c ~ +85 c
a25lq080 series (april, 2016, version 1.0) 54 amic technology corp. package information p-dip 8l outline dimensions unit: inches/mm dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.180 - - 4.57 a 1 0.015 - - 0.38 - - a 2 0.128 0.130 0.136 3.25 3.30 3.45 b 0.014 0.018 0.022 0.36 0.46 0.56 b 1 0.050 0.060 0.070 1.27 1.52 1.78 b 2 0.032 0.039 0.046 0.81 0.99 1.17 c 0.008 0.010 0.013 0.20 0.25 0.33 d 0.350 0.360 0.370 8.89 9.14 9.40 e 0.290 0.300 0.315 7.37 7.62 8.00 e 1 0.254 0.260 0.266 6.45 6.60 6.76 e 1 - 0.100 - - 2.54 - l 0.125 - - 3.18 - - e a 0.345 - 0.385 8.76 - 9.78 s 0.016 0.021 0.026 0.41 0.53 0.66 notes: 1. dimension d and e 1 do not include mold flash or protrusions. 2. dimension b 1 does not include dambar protrusion. 3. tolerance: 0.010? (0.25mm) unless otherwise specified.
a25lq080 series (april, 2016, version 1.0) 55 amic technology corp. package information sop 8l (150mil) outline dimensions unit: mm h e d a a 1 e b l 8 ~ 0 e symbol dimensions in mm a 1.35~1.75 a 1 0.10~0.25 b 0.33~0.51 d 4.7~5.0 e 3.80~4.00 e 1.27 bsc h e 5.80~6.20 l 0.40~1.27 notes: 1. maximum allowable mold flash is 0.15mm. 2. complies with jedec publication 95 ms ?012 aa. 3. all linear dimensions are in millimeters (max/min). 4. coplanarity: max. 0.1mm
a25lq080 series (april, 2016, version 1.0) 56 amic technology corp. package information sop 8l (209mil) outline dimensions unit: mm e 4 1 e b 85 d a 2 a a 1 l e 1 0.25 gage plane seating plane c dimensions in mm symbol min nom max a 1.75 1.95 2.16 a 1 0.05 0.15 0.25 a 2 1.70 1.80 1.91 b 0.35 0.42 0.48 c 0.19 0.20 0.25 d 5.13 5.23 5.33 e 7.70 7.90 8.10 e 1 5.18 5.28 5.38 e 1.27 bsc l 0.50 0.65 0.80 0 - 8 notes: maximum allowable mold flash is 0.15mm at the package ends and 0.25mm between leads
a25lq080 series (april, 2016, version 1.0) 57 amic technology corp. package information wson 8l (6 x 5 x 0.8mm) outline dimensions unit: mm/mil 1 4 58 0.25 c 0.25 c e d e 2 d 2 e b 8 l a 1 a 3 a 0.10 // c y c seating plane pin1 id area 5 6 7 14 3 2 c0.30 dimensions in mm dimensions in mil symbol min nom max min nom max a 0.700 0.750 0.800 27.6 29.5 31.5 a 1 0.000 0.020 0.050 0.0 0.8 2.0 a 3 0.203 ref 8.0 ref b 0.350 0.400 0.480 13.8 15.8 18.9 d 5.900 6.000 6.100 232.3 236.2 240.2 d 2 3.200 3.400 3.600 126.0 133.9 141.7 e 4.900 5.000 5.100 192.9 196.9 200.8 e 2 3.800 4.000 4.200 149.6 157.5 165.4 l 0.500 0.600 0.750 19.7 23.6 29.5 e 1.270 bsc 50.0 bsc y 0 - 0.080 0 - 3.2 note: 1. controlling dimension: millimeters 2. leadframe thickness is 0.203mm (8mil)

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